1. Field of the Invention
The present invention generally relates to a method for manufacturing semiconductor devices. More particular, the present invention relates to a method for manufacturing a single-sided buried strap in semiconductor devices.
2. Description of Related Arts
Dynamic random-access memory (DRAM) cells are composed of two main components, a storage capacitor that is used to stores electronic charge and an access transistor that is used to transfer the electronic charge to and from the storage capacitor. The storage capacitor may be either planar on the surface of the semiconductor substrate or trench etched into the semiconductor substrate. In the semiconductor industry where there is an increased demand for memory storage capacity accompanied with an ever decreasing chip size, the trench storage capacitor layout is favored over the planar storage capacitor design because this particular setup results in a dramatic reduction in the space required for the capacitor without sacrificing capacitance.
A very important and extremely delicate element in the DRAM cell is the electrical connection made between the trench storage capacitor and the access transistor. Such a contact is often referred to in the art as a buried strap formed at the intersection of one electrode of the storage trench capacitor and one source/drain junction of the access transistor. Referring to FIGS. 1A–1C, a conventional method for manufacturing a buried-strap at the intersection of the trench storage capacitor and the access transistor is schematically illustrated. By the masking of a patterned silicon nitride (Si3N4) pad layer 102, a trench 104 is formed into a semiconductor substrate 100 using dry etching techniques well known to those skilled in the art. An isolation collar 106 is formed on lower sidewalls of the trench 104 as shown in FIG. 1A. A layer of doped polysilicon 108 is sequentially filled into the lower portion of the trench 104, which is followed by conformal formation of a silicon nitride layer 110 and an amorphous silicon layer 112. By a tilt angle, impurities 114 are implanted into a portion of the amorphous silicon layer 112. On account of etch selectivity between impurity-containing and undoped portions of the amorphous silicon layer, the impurity-containing portion of the amorphous silicon layer 112 remains after an etch process is applied to remove the undoped portion of the amorphous silicon layer 112 as shown in FIG. 1B. Then, the silicon nitride layer 110 and the polysilicon layer 108 are sequentially patterned using the amorphous silicon layer as a masking film such that a portion of the isolation collar 106 can be exposed. In FIG. 1C, a layer of insulative material 116 is formed on a portion of upper sidewalls of the trench 104 using deposition and etching, both of which are well-known to those skilled in the art. The amorphous silicon layer 112 and the silicon nitride layer 110 are thereafter removed such that a buried strap 118 is formed.
The contact resistance of the buried strap is a critical parameter for DRAM cells. However, the contact resistance of the buried strap in accordance with the conventional method cannot be well controlled.